Non-volatile semiconductor memory devices based on metal-oxide-semiconductor field effect transistors (MOSFETS) were first proposed in 1967 (see Sze, "Physics of Semiconductor Devices" (Wiley-Interscience, pages 496-506, 2d Ed. 1981). These devices store a bit of information as the presence or absence of a quantity of electrical charge on a floating gate that is located so that the charge affects the threshold voltage of a MOSFET. Currently/ MOSFET non-volatile memory devices include EPROMS, EEPROMS and Flash EEPROMS.
Flash EEPROMS are hybrids that program in the manner of either EPROMS (avalanche-injection) or EEPROMS (tunneling) and erase in the manner of EEPROMS (tunneling) but with the erasure generally limited to bulk electrical erasure of the entire memory analogous to the ultraviolet light erasure of an EPROM. Flash EEPROMS have the advantage of smaller cell size in comparison with standard EEPROMS because the cells are not erased individually. Instead, the array of cells is erased in bulk.
Flash EEPROMS, which use the merged pass gate structure to turn off the channel if the floating gate has been overerased, are very sensitive to alignment. If the floating gate and control gate of one of these flash EEPROM cells are misaligned, the length of the channel controlled by the control gate will increase or decrease, and the remainder of the channel length (controlled by the floating gate) will correspondingly decrease or increase, thereby causing variations in the reading, writing and programming characteristics of the cell. It has therefore become desirable to devise an EEPROM or merged FAMOS device which can be fabricated without alignment sensitivity.